Static random access memory (SRAM) is a type of semiconductor memory having an array of memory cells, where each memory cell stores one bit of information as a logic “1” state or a logic “0” state. In a conventional SRAM, each memory cell includes a one-bit memory element (bit-element), usually a bistable latch, that is capable of maintaining a logic state as long as power is maintained to the SRAM. SRAMs are widely used where high-speed memory is required, for example as high-speed cache memories in personal computers.
In conventional memory cell arrays, data is read out from a specified memory cell by activating a corresponding word line, and then discharging a voltage from the selected memory cell through a corresponding bit line to a read circuit. This operation is ultimately limited by the amount of current that can pass through the memory cell, where higher currents afford greater speeds. However, efforts to improve memory density have resulted in a reduction of the scale of bit-elements in the memory cells. The smaller memory cell structures require that the bit cell discharge current be reduced, consequently resulting in a reduction in bit-line discharge speed. Thus, memory access speed is adversely affected by reduction in the size of memory cell array components.